This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-181687, filed Jun. 28, 1999, the entire contents of which are incorporated herein by reference.
The present invention generally relates to a method of manufacturing semiconductor devices, and more particularly relates to a method of manufacturing low power dissipation semiconductor power devices.
Some of the low power dissipation semiconductor power devices of the prior art have a junction structure (hereafter referred to as xe2x80x9csuper junctionxe2x80x9d) consisting of a vertical junction group where a first conductivity-type region and a second conductivity-type region are alternatively arranged vertically to the surface of a silicon substrate.
There is a prior method of creating such super junction structure by repeating Nxe2x88x92 epitaxial growth and ion implantation. FIG. 1 provides a brief explanation of this manufacturing process. In FIG. 1, a flow of the manufacturing process is shown in the right-hand part and cross sections of the silicon substrate at each step in the left-hand part.
As shown in FIG. 1, an N+ silicon substrate 101 is prepared and on that an Nxe2x88x92 epitaxial layer 102 is grown. Then boron-ions are implanted by the use of an ion implantation mask (not shown) to form P+ regions 103 in the Nxe2x88x92 epitaxial layer 102. Subsequently, by the use of an inverted mask of the ion implantation mask, phosphorous ions are implanted in a region adjacent to the P+ regions 103 to form N+ regions 104.
These ion-implanted regions are activated by annealing (not shown) to provide the P+ regions 103 and N+ regions 104. Annealing can be performed either after each ion implantation or after all the implantations have been completed. In this way, a PN junction plane is formed as part of a super junction consisting of PN junctions vertically arranged to the surface of an epitaxial layer.
Next, another Nxe2x88x92 epitaxial layer 102 is grown and, as shown in the right-hand part of FIG. 1, the steps from boron implantation to Nxe2x88x92 epitaxial growth are repeated. Then a vertical super junction is formed where PN-junction planes are alternatively created in the vertical direction to the wafer surface.
The N+ silicon substrate 101, which was used at an early step, will be a drain region of the low power dissipation semiconductor power device. Since the manufacturing method to be employed in the processes after the formation of a super junction is described later in FIG. 6D, detail explanation is not given here.
If a low power dissipation semiconductor power device having this super junction structure is manufactured to which high voltages are applied, since drain junction planes are formed by P+ and N+ regions that extend vertically to the wafer surface and a current path is created in the N+ layer in the inner bulk region of the silicon substrate, the low power dissipation semiconductor power device of NMOS-type shows a low ON resistance and a high drain withstand voltage.
A shortcoming in the above prior art is that such manufacturing method of repeating the epitaxial growth process to create low power dissipation semiconductor power devices is costly, difficult to implement and not suitable for mass production.
The present invention has been made to solve the above problem and its principal object is to provide a method of manufacturing low power dissipation semiconductor power devices having the super junction structure.
The present invention employs not the low-yield epitaxial growth process but a method suitable for mass production by irradiating particle beams such as an ion beam and a neutron beam onto semiconductor substrates to provide low power dissipation semiconductor power devices having the super junction structure at low cost and with ease.
To be more specific, the present invention is a semiconductor device manufacturing method of forming a second conductivity-type region by irradiating impurity ions selectively onto a first conductivity-type semiconductor substrate, wherein the above impurity ion irradiated region is restricted by a shield mask that intercepts the impurity ions and the acceleration energy of impurity ions is controlled so that the impurity concentration in the second conductivity-type region may be uniform along the direction of irradiation.
The present invention is a semiconductor device manufacturing method of forming at least one of a first conductivity-type region and a second conductivity-type region in the semiconductor substrate by irradiating impurity ions selectively onto the semiconductor substrate, wherein the impurity concentration is uniform along the direction of irradiation in the first and second conductivity-type regions and the impurity ion acceleration energy and the area of irradiated region are controlled to make the cross-sectional shape and the cross-section area of each of the first and second conductivity-type regions on planes vertical to the irradiation direction uniform along the direction of irradiation.
In a preferred embodiment of the present invention, the area of irradiated region is controlled by an electric sweeping or magnetic sweeping of the impurity ion beam, or by movement of the semiconductor substrate. In the control of the ion acceleration energy and the area of the irradiated region, the area of the irradiated region is changed according to changes in the ion acceleration energy.
Further, in another preferred embodiment of the present invention, the area of the irradiated region is controlled with a shield mask intercepting the impurity ions, and the acceleration energy and the area of the irradiated region are controlled by changing the aperture area of the mask according to changes in the acceleration energy.
The present invention is a semiconductor device manufacturing method of forming a first and second conductivity-type regions by irradiating impurity ions selectively onto a semiconductor substrate; wherein two shielding masks in a reversed imaging relation to each other are used to restrict the impurity ion irradiated regions so that the cross-sectional shape and the cross-section area of the first and second conductivity-type regions on planes vertical to the irradiation direction may be uniform in the direction of irradiation; and the impurity ion acceleration energy is controlled to make the impurity concentration in the first and second conductivity-type regions uniform in the direction of irradiation.
The present invention is a semiconductor device manufacturing method of forming an N+ region by selectively irradiating a neutron beam onto a P+ semiconductor ingot, wherein the incident angle of the neutron beam is collimated so that the cross-sectional shape and the cross-section area of the N+ region may be uniform in the direction of irradiation and so that the impurity concentration in the N+ region may be uniform in the direction of irradiation.
In a preferred embodiment of the present invention, the P+ ingot is made of one of silicon, germanium and silicon carbide, and the incident angle of the neutron beam is parallel to the direction of a growth axis of the P+ semiconductor ingot.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of the present invention which proceeds with reference to the accompanying drawings.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.